DK-DEV-5SGXEA7N【PDF 183/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51007

2014.01.10

Soft-CDR Mode

6-27

? Guideline: Use PLLs in Integer PLL Mode for LVDS on page 6-8

Soft-CDR Mode

The Stratix V LVDS channel offers the soft-CDR mode to support the GbE and SGMII protocols. A receiver

PLL uses the local clock source for reference.

The following figure shows the soft-CDR mode datapath. In SDR and DDR modes, the data width from the

IOE is 1 and 2 bits, respectively.

Figure 6-26: Receiver Datapath in Soft-CDR Mode

IOE

10 bits

maximum

data width

rx_out

10

IOE supports SDR, DDR, or non-registered datapath

2

Deserializer Bit Slip

Synchronizer

LVDS Receiver

DPA Circuitry

+

–

rx_in

10

FPGA

DOUT

DIN

DOUT

DIN

DOUT

DIN

Retimed

Data

DIN

Fabric

2

diffioclk

DPA Clock

(LOAD_EN,

rx_divfwdclk

rx_outclock

diffioclk)

Clock Mux

3

(DPA_LOAD_EN,

DPA_diffioclk, rx_divfwdclk)

3 (LVDS_LOAD_EN,

LVDS_diffioclk, rx_outclock)

8 Serial LVDS

Clock Phases

DPA Clock Domain

LVDS Clock Domain

Fractional PLL

rx_inclock

Note: All disabled blocks and signals are grayed out

In soft-CDR mode, the synchronizer block is inactive. The DPA circuitry selects an optimal DPA clock phase

to sample the data. Use the selected DPA clock for bit-slip operation and deserialization. The DPA block

also forwards the selected DPA clock, divided by the deserialization factor called rx_divfwdclk , to the FPGA

fabric, along with the deserialized data. This clock signal is put on the periphery clock (PCLK) network.

If you use the soft-CDR mode, do not assert the rx_reset port after the DPA has trained. The DPA

continuously chooses new phase taps from the PLL to track parts per million (PPM) differences between

the reference clock and incoming data.

You can use every LVDS channel in soft-CDR mode and drive the FPGA fabric using the PCLK network in

the Stratix V device family. The rx_dpa_locked signal is not valid in soft-CDR mode because the DPA

continuously changes its phase to track PPM differences between the upstream transmitter and the local

receiver input reference clocks. The parallel clock, rx_outclock , generated by the left and right PLLs, is also

forwarded to the FPGA fabric.

Related Information

Periphery Clock Networks on page 4-4

Provides more information about PCLK networks.

High-Speed Differential I/O Interfaces and DPA in Stratix V Devices

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